The inventors have observed that scaling semiconductor devices by simply shrinking the device structure often does not produce acceptable results at small dimensions. In NAND flash memory devices, when a feature, such as a tunnel oxide layer, an inter polysilicon dielectric (IPD) cap, or the like is scaled, undesired leakage can occur between, for example, a substrate and a floating gate, a floating gate and a control gate, or the like. For example, the inventors have observed that when scaling flash memory devices, conformal nitride layers used to form conventional inter polysilicon dielectric caps may electrically couple adjacent floating gates, thereby causing leakage between adjacent floating gates, thus decreasing device performance.
Accordingly, the inventors have provided improved semiconductor devices using an interlayer polysilicon dielectric cap and methods of making thereof.